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| HCF4033B DECADE COUNTER/DIVIDER WITH DECODED 7-SEGMENT DISPLAY OUTPUT AND RIPPLE BLANKING s s s s s s s s s s COUNTER AND 7-SEGMENT DECODING IN ONE PACKAGE EASILY INTERFACED WITH 7-SEGMENT DISPLAY TYPES FULLY STATIC COUNTER OPERATION : DC TO 6MHz (Typ.) AT VDD = 10V IDEAL FOR LOW POWER DISPLAYS RIPPLE BLANKING AND LAMP TEST QUIESCENT CURRENT SPECIF. UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4033BEY HCF4033BM1 T&R HCF4033M013TR DESCRIPTION The HCF4033B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4033B consists of a 5-stages Johnson decade counter and an output decoder which converts the Johnson code to a 7 segment decoded output for driving one stage in a numerical display. This device is particularly advantageous in display applications where low power dissipation and/or low package count are PIN CONNECTION important. This device has CLOCK, RESET, CLOCK INHIBIT, RIPPLE BLANKING, LAMP TEST input, CARRY OUT, RIPPLE BLANKING and 7 DECODED outputs (a to g). A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (COUT) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. September 2001 1/11 HCF4033B The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on selection. This device has provisions for automating blanking of the non-significant zeros in a multi digit decimal number which results in a easily readable display consistent with normal writing practice. For example, the number 0050.07000 in an eight digit display would be displayed as 50.07. Zero suppression on the integer side is obtained by connecting the RBI terminal of the HCF4033B associated with the most significant digit in the display to a low level voltage and connecting the RBO terminal of that stage to the RBI terminal of the HCF4033B in the next lower significant position in the display. This procedure is continued for each succeeding HCF4033B on the integer side of the display. On the fraction side of the display the RBI of the INPUT EQUIVALENT CIRCUIT HCF4033B associated with the least significant bit is connected to a low level voltage and the RBO of that HCF4033B is connected to the RBI terminal of the HCF4033B in the next more significant bit position. Again, this procedure is continued for all HCF4033B's on the fraction side of the display. In a purely fractional number the zero immediately preceding the decimal point can be displayed by connecting the RBI of that stage to a high level voltage (instead of to the RBO of the next more significant stage). For example : optional zero 0.7346. Likewise, the zero in a number such as 763.0 can be displayed by connecting the RBI of the HCF4033B associated with it to a high level voltage. Ripple blanking of non-significant zeros provides an appreciable savings in display power. The HCF4033B has a LAMP TEST input which, when connected to a high level voltage, overrides normal decoder operation and enables a check to be made on possible display malfunctions by putting the seven outputs in the high state. PIN DESCRIPTION PIN No 1 10, 12, 13, 9, 11, 6, 7 2 15 3 5 4 14 8 16 SYMBOL CLOCK a to g CLOCK INHIBIT RESET RIPPLE BLANKING IN CARRY OUT RIPPLE BLANKING OUT LAMP TEST VSS VDD NAME AND FUNCTION Clock Input 7 - Segments Decoded Outputs Clock Inhibit Input Reset Input Ripple Blanking Input Carry Out Output Ripple Blanking Output Lamp Test Input Negative Supply Voltage Positive Supply Voltage 2/11 HCF4033B FUNCTIONAL DIAGRAM LOGIC DIAGRAM 3/11 HCF4033B TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C 4/11 HCF4033B DC SPECIFICATIONS Test Conditions Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) IO VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 0.1 7.5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit IL Quiescent Current A VOH High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current VOL VIH VIL <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 V V V V IOH IOL Output Sink Current Input Leakage Current Input Capacitance 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 mA mA A pF II CI any input any input The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 5/11 HCF4033B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns) Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 250 100 75 350 125 90 100 50 25 5 11 16 110 50 40 Unlimited Max. 500 200 150 700 250 180 200 100 50 Unit CLOCKED OPERATION tPLH tPHL Propagation Delay Time (Carry Out Line) tPLH tPHL Propagation Delay Time (Decoded Out Lines) tTHL tTLH Transition Time (Carry Out Line) fCL (1) Maximum Clock Input Frequency Clock Pulse Width ns ns ns 2.5 5.5 8 MHz 260 100 80 tWC ns tr , tf Clock Input Rise or Fall Time s RESET OPERATION tPLH tPHL Propagation Delay Time (Carry Out Line) tPLH tPHL Propagation Delay Time (Decoded Out Lines) tWR Reset Pulse Widht trem Reset Removal Time 275 120 80 300 125 90 100 50 25 0 0 0 550 240 160 600 250 180 120 100 50 30 15 10 ns ns ns ns (*) Typical temperature coefficient for all VDD value is 0.3 %/C. (1) Measured with respect to carry output line. 6/11 HCF4033B TYPICAL APPLICATIONS Interfacing with Filament Fluorescent Display Detail of Typical Flip-flop Stage Interfacing with LED Displays (display common anode) Interfacing with LED Displays (display common cathode) Interfacing with NIXIE Tube 7/11 HCF4033B TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50) 8/11 HCF4033B Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 9/11 HCF4033B SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 10/11 HCF4033B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com 11/11 |
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